1. Field of the Invention
The invention relates generally to electronic circuits, and more particularly to systems and methods for reducing timing variations of signals that result from coupling capacitance between signal lines.
2. Related Art
With advancements in computer-related technologies, there is constantly a demand for faster and smaller devices. In order to make these devices smaller and faster, it is necessary to make the components that form the devices physically smaller. Decreasing the size of these components, however, can result in problems that prevent the devices from operating more quickly, and may even cause the devices to malfunction.
As the size of electronic components decreases, the size and spacing (pitch) of the wires connecting these components also decreases. As the pitch of the wires in an electrical circuit decreases, the coupling capacitance of these wires increases. The increased coupling capacitance in turn results in increased interference between the wires. Interference between signals on adjacent wires can cause signal transitions to occur more quickly or more slowly, depending upon the particular signals on each of the wires.
The time-varying signals carried on a wire in a computer or other digital device represent binary values (i.e., a 0 or a 1.) In order to interpret the sequence of binary values represented by the time-varying signal on a particular wire, it is important to know the timing of the signal. In other words, it is important to know when the signal may be transitioning between values, and when the signal is stable and can be interpreted as either a 0 or a 1. When the time required for the signal to make transitions between values changes because of interference between signals on adjacent wires, the timing constraints on the signal must be relaxed in order to ensure that the signal is not too close to a transition when it is being interpreted as a binary value.
Binary signal lines often have in-line buffers (e.g., inverters) to strengthen the corresponding signals as they traverse the length of the lines. Conventional devices sometimes attempt to minimize the interference between adjacent signal lines by providing multiple in-line inverters in each of the signal lines, and staggering the positions of the inverters. As a result, over the length of a segment of a particular signal line, the neighboring signal lines have one value for half of the length, and the opposite value for the other half of the length. This is illustrated in FIG. 1.
Referring to FIG. 1, portions of three adjacent signal lines are shown. Each of lines 110, 120 and 130 has a pair of inverters. (Each line may include other inverters, but these are not shown for purposes of clarity.) It can be seen that the inverters in each line are positioned halfway between the inverters of the adjacent lines. As a result, the transitions on adjacent lines are also staggered and therefore cause less interference between adjacent lines and less variations in signal timing.
This conventional solution, however, may have several problems. For example, this solution involves the use of more inverters than are typically necessary simply to drive the signals on the respective lines. Because additional components are necessary, additional space is required in order to provide these components. Providing this additional space may be difficult and/or expensive. Further, because different signal lines may have different lengths, this solution may result in different loads on the signal lines. This results in even greater variations in the effective lengths of the signal paths which causes additional timing problems.
It would therefore be desirable to provide systems and methods for reducing interference between signal lines which causes variations in the timing of signal transitions, without incurring the problems associated with conventional solutions.